ALDEC has released version 2012.12 of its ALINT static design analysis and checking solution for ASIC and FPGA.
According to the company, the new version of ALINT decreases verification time by identifying critical issues early in the RTL design phase.
ALINT 2012.12 delivers performance improvements, a team-based task management utility, and a new premium rule library that includes checkers to optimise routing resources in designs targeting today’s largest FPGAs.
According to Aldec, while each device family is unique as a place and route target, mismanagement of routing resources negatively impacts resource utilisation, performance and power.
Within the RTL, routing-unaware design styles limit choices for the place and route tools later in the design cycle. This results in additional routing capacitance and delay, and consequently increased power and impaired performance.
Routing-aware design techniques as enabled by ALINT improve routing utilisation and allow place and route applications to consume less of the target device and produce better quality results.
Three core issue types addressed by the new checkers implemented in ALINT 2012.12 premium rule library are:
- Logic placement at different levels of design hierarchy (hierarchical design)
- Suboptimal cross-hierarchy interconnections that increase fanout
- I/O port registering issues
The guidelines supported in ALINT’s premium rule library enable logic synthesis and place and route tools to provide more efficient chip utilisation.