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RENESAS Electronics says it has developed a new camera video processing circuit block for autonomous driving, boasting low latency, high performance and low power consumption.
The new video processing circuit block for use in automotive computing system-on-chips (SoCs) will help realise the autonomous driving future, claims the Japan-based company.
Automotive computing SoCs for autonomous vehicles are required to integrate the functionality of both in-vehicle infotainment systems and driving safety support systems, and to operate both in parallel.
To ensure safe operation, driving safety support systems must be able to process video data from vehicle cameras with low latency, so the driver is notified of issues rapidly.
This can be very challenging: driving safety support systems must perform cognitive processing based on video transferred from vehicle cameras, identifying obstacles, monitoring the status of the driver, and anticipating and avoiding hazards.
Besides the AI-driven functionality, the system must also handle the encoding and decoding of video data transferred from vehicle cameras into video streams, and prepare the footage from wide-angle cameras by correcting for distortion.
All of these tasks, involving the processing of large amounts of video data, must be carried out without delays and instability. And this does not include the infotainment aspects of automotive systems, which require high speed connectivity to external devices and services, and the streaming of video into in-vehicle displays.
The newly developed video processing circuit block handles can perform video processing in real time on large volumes of video data with low power consumption and without imposing any additional load on the CPU and graphics processing unit (GPU), which are responsible for autonomous vehicle control.
Renesas has manufactured prototypes of the new video processing circuit block using a 16 nanometer (nm) FinFET process. In addition to 70ms-latency processing of vehicle camera video, it delivers industry-leading Full-HD 12-channel video processing with only 197 mW power consumption.
Features of the newly developed video processing circuit block include:
- Synchronous operation among video processors, combined with pipeline operation, for video decoding and distortion correction with 70ms latency
- 17 video processors of six different types, optimized for automotive computing systems to deliver industry-leading Full-HD 12-channel performance
- Combination of two types of data compression, lossless compression and lossy compression, to reduce memory bandwidth by 50 percent and achieve Full-HD 12-channel processing with industry-leading low power consumption of 197 mW