Over the past 25 years, that I have been involved in high-speed multilayer PCB design, much has changed. Particularly, advances in lithography enables IC manufacturers to ship smaller and smaller dies on chips. In 1987 we thought that 0.5 micron technology was the ultimate but today 28nm technology is common. Also, power consumption, in FPGA’s, has become a primary factor for FPGA selection. Whether the concern is absolute power consumption, battery life, thermal challenges, or reliability, power consumption is at the centre of it all. In order to reduce power consumption, IC manufacturers have moved to lower core voltages and higher operating frequencies which of course mean faster edge rates.
However, faster edge rates cause reflections and signal quality problems. So although the package and your clock speed have not changed a problem may exist for legacy designs. The enhancements in driver edge rates have a significant impact on signal quality, timing, crosstalk, and EMC. So whether you like it or not – you are now a high-speed designer.
Figure 1. Edge rate changes over the past 25 years
Figure 1 illustrates the change in edge rates over the years – from 30ns back in 1985 to less than 1ns in 2010. The faster edge rate for the same frequency and same length trace creates ringing in the un-terminated transmission line. This also has a direct impact on radiated emissions. Figure 2 shows the massive increase in emissions from the slowest to fastest rise time. When dealing with 1ns rise times, the emissions can easily exceed the FCC/CISPR Class B limits for an un-terminated transmission line.
Figure 2. Radiated emissions from the 30 ns edge rate (left) and 1ns (right)
Also, today’s high-density, high-performance FPGA’s typically require a number of different power supplies (for example 1.2V, 1.35V, 1.5V, 1.8V, 2.5V and 3.3V for a Virtex-7) to power the core and I/O. These are best sourced from a switch mode power supply. Core current consumption depends upon utilization of the part (such as clock speed and internal elements used), but maximum values range from 1.5A to 10A. Current consumption for the I/Os depends on the voltage and the utilization of the I/O elements; however, for all I/O banks operating together, the maximum current demand can exceed 10A.
Another power management consideration that needs to be addressed is the monotonic rise of voltage in the core and I/O to their steady state levels. This consideration is critical for the correct operation of the FPGA because if the voltage sags during boot-up, the device may not reset. While many power supplies take this requirement into consideration, it is recommended to further support this requirement by the use of adequate bulk capacitance in the Power Distribution Network (PDN).
Figure 3. The PDN of a 1.8V DDR2 supply is analyzed by the ICD PDN Planner
Figure 3 illustrates the combined effect of the Voltage Regulator Module (VRM), 10uF bulk bypass, 100nF decoupling capacitors, the plane resonance of the board and capacitor mounting/loop inductance for a typical DDR2, 1.8V supply. The objective is to keep the effective impedance as low as the target impedance (horizontal line) up to the fundamental frequency of the clock (400 MHz vertical line).
In the above case, there is an anti-resonance peak at 158 MHz, but fortunately that is well below the fundamental clock frequency of 400MHz. Also, one needs to keep the odd harmonics in mind. If the plane resonance appears at the 3rd (1.2GHz), 5th (2GHz) or 7th (2.8GHz) harmonic, there could be an issue. In this case, there is a peak at the 3rd harmonic so this needs to be addressed by changing the 1.8V plane size to reduce the resonance as the frequency approaches half wave length.
Apart from PDN planning, the board stackup integrity is the other issue that is most often over-looked when designing a high-speed board. The majority of designers leave the stackup planning to deal with at design completion – along with fabrication deliverables.
Before starting a PCB design, you need to plan the PCB stackup and ensure that the selected substrate materials are available from your chosen fabrication — a step that is regularly missed. Changing the stackup towards the end of the design process could mean changing trace widths and clearances to achieve the correct impedance, which could create a lot of unnecessary work and delay.
If you use the same materials that the PCB fabrication shop stocks, to build our stackup, then the impedance will be more accurate. If you just choose a convenient number, for core thickness, for example, then there may be up to 3% difference from what is available; hence, the impedance will vary by 3%.
The most widely used dielectric material is FR4 and may be in the form of core or prepreg (pre-impregnated) material. Isola’s top selling materials are FR406 and FR408. While FR406 sets the industry standard for basic multilayer PCB fabrication, FR408 is a high-performance FR4 epoxy dielectric for improved signal performance. Its low dielectric constant and low dissipation factor make it an ideal candidate for broadband circuit designs requiring fast signal speeds or improved signal integrity. Also, the high glass transition temperature makes it compatible with ROHS compliant components and most FR4 processes.
The configuration of the PCB Stackup depends on many factors but whatever the requirements one should ensure that the following rules are followed in order to avoid a possible debacle:
- All signal layers should be adjacent to and closely coupled to a reference plane, creating a clear return path and eliminating broadside crosstalk.
- There is good interplane capacitance to reduce inductance at high frequencies.
- High speed signals should be routed between the planes to reduce radiation.
- The substrate should be symmetrical with an even number of layers. This prevents the PCB from warping during manufacture and reflow.
- The stackup should accommodate a number of different technologies.
- Cost (the Boss’s most important design parameter) should also be addressed.
Figure 8 shows a typical 8 layer stackup that can used for DDR2 designs. It is important to avoid adjacent layer crosstalk by having each signal in a stripline configuration between planes. Also, the high-speed signals should only be routed on these internal stripline layers to avoid microstrip radiation. The stackup should accommodate 50 ohm single ended, 100 ohm differential and 90 ohm differential impedance for USB (if present).
Figure 4. A typical 8 layer stackup simulated by the ICD Stackup Planner
As previously mentioned, it is important to keep the AC impedance of the PDN as low as possible over the entire frequency range. Decoupling and bypass capacitors are only effective up to about 400MHz. So to provide suppression at higher frequencies we need to use interplane capacitance. This is achieved by using a thin dielectric between the central power planes.
The power to ground plane capacitance provides an ideal capacitor in that it has no series lead inductance and no equivalent series resistance (ESR). This helps reduce noise at extremely high frequencies. Good interplane capacitance can be achieved by using 4mil plane spacing resulting in 241pF/in2. The higher the better. Whereas, 10mil spacing will only achieve 96.75pF/in2 and 60mil a dismal 16pF/in2.
Now that the two basic but most important part of the design is planned – the PDN and the stackup, a pre-layout analysis is preformed to establish placement and routing rules.
Flight time delay and skew are key pillars in high speed PCB design signal integrity. One of the driving factors for flight time and skew performance is the placement of components. Maximum placement refers to the placement in which the distances between the devices are the maximum distance permitted. Controlling the maximum placement of devices, combined with the assumption that good general design practices are adhered to, limits maximum trace delay to roughly the longest Manhattan distance of the signals contained in a specific clock domain.
Why the longest Manhattan distance? This is due to skew matching requirements: All of the shorter nets in a clock domain must be lengthened to skew match to the longest run length. Therefore, flight time and skew—for an entire clock domain—are governed by the maximum placement, along with the routing rules that constrain the matching of the trace lengths and differential pairs.
In the classic high-speed design flow, timing specifications simulation results are compared to determine placement and routing constraints. Given a length constraint, a designer can control signal integrity by controlling the PCB trace topology of the various parts of an interface. Included in this topology are any terminations.
Figure 5. Skew of clock to address, control and command signals of DDR3 memory
Figure 5 illustrates the timing of the clock compared to the address, control and command signals of a DRR3 memory design. The skew can be up to 200ps for DDR3-800. Also, the skew between data lanes and data strobes should be kept to less than 125ps and the eyes should be wide open. DDR3 is much easier to route, in fact, than DDR2 as leveling can be used to synchronize the delay of groups of signals.
Unfortunately, board-level simulation is engaged too often towards the end of the design cycle. Ideally, the simulation should be done during the design process or even better still – before a single chip is placed on the board, to ensure design integrity.
A preliminary batch mode simulation is first completed on the design. Default IC characteristics, crosstalk of 150mV maximum and EMC to FCC/CISPR Class A and B are setup in the simulator. The batch mode simulation automatically scans large numbers of nets on an entire PCB, flagging Signal Integrity, Crosstalk and EMC hot spots.
The post-layout simulation analysis can then be prepared using supplied specifications. This report contains the results of the extensive Interactive Board Level Simulation which takes the analysis to the next level – simulating trouble spots identified by the batch analysis in order to further resolve the issues with greater accuracy.
The critical signals are again checked now that the physical information is obtained from the PCB data base (eg trace lengths, clearances, vias etc) to ensure that the design complies to specification. Figure 6 measures the DQ0 signal at the load. The horizontal noise (top and bottom of the waveform) indicates AC timing noise or jitter outside the differential peak to peak voltage.
Figure 6. Measuring the DQ0 waveform at the load
Figure 7 Crosstalk on long parallel trace segments
Crosstalk is typically picked up on long parallel trace segments. These can be on the same layer as in Figure 7, but may also be broadside coupled from the adjacent layer. It is for this reason that orthogonal routing is recommended on adjacent layers (between planes) to minimize the coupling area. This will not occur with the stackup illustrated in Figure 4, because there is only one signal layer between the planes – so this design is very safe as far as broadside crosstalk is concerned.
High-speed boards can be designed to work right the first time, with little additional effort, providing you follow a tried and proven process that results in a reliable, manufacturable design that conforms to specifications and is produced on time and to budget.
We all know that simulation tools are not cheap and then there is a learning curve associated with complex software not to mention that the Engineer needs to have years of experience analyzing high speed designs. By utilizing a PCB Board Level Simulation Service, you can be assured that your PCB will be reliable, manufactureable, conforms to specifications and passes the relevant compliancy tests saving you time, money and frustration for a fraction of the cost of board iterations and multiple compliancy testing. Plus, the simulation can be done before the design is finalized (before Gerber output or even earlier in the design process) to further reduce production time and costs.
Advanced Design for SMT – Barry Olney
Intro to Board-Level Simulation and the PCB Design Process – Barry Olney
PCB Design Techniques for DDR, DDR2 & DDR3, Part 1 & 2 – Barry Olney
The ICD Stackup and PDN Planner can be downloaded from www.icd.com.au
Barry Olney is the Managing Director of In-Circuit Design Pty Ltd (ICD), Australia. The company developed the ICD Stackup Planner and ICD PDN Planner software, is a PCB Design Service Bureau and specializes in board level simulation.