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RESEARCHERS at UNSW and the University of Melbourne have designed a 3D silicon chip architecture based on single atom quantum bits, providing a blueprint to build a large-scale quantum computer.
Scientists and engineers from the Australian Research Council Centre of Excellence for Quantum Computation and Communication Technology (CQC2T), headquartered at UNSW, are working to develop a scalable quantum computer in silicon.
Already, the researchers have demonstrated a unique fabrication strategy, allowing them to build devices in silicon at the atomic-scale. They have also developed the world’s most efficient quantum bits in silicon using either the electron or nuclear spins of single phosphorus atoms.
The question that remained had to do with scaling up the developments thus far to build a functional unit. For this, the architecture of the quantum computer is key — how, for example, to precisely control multiple qubits in parallel, across an array of many thousands of qubits, and constantly correct for ‘quantum’ errors in calculations?
In a study published today in Science Advances, the CQC2T team describes a new silicon architecture, which uses atomic-scale qubits aligned to control lines inside a 3D design.
UNSW Scientia Professor Michelle Simmons, study co-author and Director of the CQC2T said that this architecture gives the researchers an endpoint to work towards.
“We now know exactly what we need to do in the international race to get there," she said.
Essentially, the researchers figured out a way to deal with errors in quantum computers, an essential achievement that may help them become the first to build a functioning quantum computer in silicon.
In the team’s conceptual design, they have moved from a one-dimensional array of qubits (a single line), to a two-dimensional array (on a plane) that is far more tolerant to errors.
This 2D qubit layer is then “sandwiched” in a three-dimensional architecture, between two layers of wires arranged in a grid.
The researchers can apply voltages to a selection of these wires to control multiple qubits in parallel, allowing operations using far fewer controls.
The architecture also allow the the researchers to perform the 2D surface code error correction protocols, where any computational errors that creep into the calculation are corrected faster than they occur.
In their paper, the team proposes a strategy to build the device, which leverages the CQC2T’s ability to fabricate devices at an atomic-scale.
They have also modelled the required voltages applied to the grid wires, needed to address individual qubits, and make the processor work.
“This architecture gives us the dense packing and parallel operation essential for scaling up the size of the quantum processor,” says Scientia Professor Sven Rogge, Head of the UNSW School of Physics. “Ultimately, the structure is scalable to millions of qubits, required for a full-scale quantum processor.”