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The University of Toronto and Fujitsu Laboratories have announced the joint development of the world’s lowest power referenceless CDR. The newly developed circuit operates with 55 per cent of the power requirements of previous technology for optical modules in Ethernet used for communication between servers and switches in datacenters.
With the spread of big data analysis and cloud services, there has been a demand for faster and denser optical modules in order to provide high data transfer capability between servers and switches, which has necessitated miniaturisation and reductions in power consumption.
To speed up and miniaturise optical modules, referenceless CDR technology has been developed that does not require a crystal oscillator to produce the standard timing. With existing referenceless CDRs, however, the circuit that detects discrepancies in the timing cycle for reading input data has high power consumption, leading to problematic heat generation and causing difficulties in increasing circuit density.
Previously, in order to detect discrepancies in the data-reading cycle, it was necessary to detect the signal four times with different timing for each bit of data, with the power consumption for each timing generator taking up a significant proportion of the power consumption of the module as a whole.
Now, the University of Toronto and Fujitsu Laboratories have developed a new timing extraction technology that can operate on the same cycle as the data transmission speed, detecting once for each bit discrepancies in the reading cycle from amplitude information in the input signal. The result is that the number of timing generators can be reduced to one-fourth that of previous architectures, successfully cutting power consumed by the optical module as a whole to about 70 per cent that of previous technologies.
This technology lowers the power consumption of optical modules, enabling high traffic transmission capability through denser implementations and thereby improving datacenter processing capability.
Details of this technology will be announced at the IEEE International Solid-State Circuits Conference 2017, which is the largest conference for semiconductor technology, being held from February 5 in San Francisco (ISSCC session numbers 6.6)