The new dimension in chip design


For the last five years or so leading processor makers such as Intel and AMD have been fighting an increasingly difficult battle to continue the decades long trend dubbed Moore’s Law.

Gordon Moore, processor-maker Intel’s founder, postulated in a paper back in 1965 that the number of transistors on a chip would double every two years (processor performance doubles roughly every 18 months because the transistors also work a little faster with each chip iteration).

Moore’s forecast has proved uncannily accurate for the last 46 years (although in recent years that has been primarily due to semiconductor companies using the ‘law’ as a benchmark for R&D targets).

Along the way challenges have arisen that threaten continuation of the trend, but each time the chipmakers have found a way round the roadblock. The latest hurdle is current leakage from devices with features so small (of the order of just 22 nm) that wayward electrons find it all too easy to go AWOL instead of sticking to the paths the designer has determined for them.

Intel’s latest chips attempt to address that problem by employing exotic materials such as Hafnium oxide and fabricating novel 3-D Tri-Gate transistors. These technologies have allowed the American company to push Moore’s Law forward for a few more years and shoehorn hundreds of millions of transistors onto its current devices.

But it can’t go on; eventually the laws of physics (specifically quantum mechanics and power-density constraints) will prevent further transistor shrinkage and chip density will reach a plateau. But the chip companies are already planning to overcome this roadblock with some lateral thinking… actually, make that vertical thinking.

Onwards and upwards

Shrinking transistor size has proven a very successful way to cram more onto a chip, but it’s not the only solution to ensure each new generation of electronics does more for less. Stacking 2D chips on top of each other to form a 3D package is another. The result is a much more powerful device but with the same footprint as a 2D die. 

Apart from the space saving, the key advantage of this technique compared to simply connecting a series of conventional devices together is that the interconnection between the layers (in the ‘z’ direction) – typically formed by through silicon vias (TSV) – is ‘on-chip’ rather than via a PCB supporting the components. TSVs are much shorter and faster than off-chip traces, maintaining the high performance of the traditional monolithic processor (see figure 1).

But there’s so much more to 3D chips than just maintaining the relentless drive to greater density. Some of these advantages are obvious – for example, using on-chip interconnection lowers power consumption by 10-to-100 times compared with off-chip traces, and parasitic capacitances are minimised helping to maintain signal integrity – but others are a little more subtle.



Figure 1: Schematic of complex 3D IC. Vertical black lines represent TSVs. (Courtesy: Cadence)


For example, using TSVs to interconnect the layers allows for the on-chip fabrication of a very large parallel bus, boosting bandwidth compared with chip-to-chip interconnection. Second, each layer can be designed at a different process node. Digital functionality, for instance, can be manufactured using high-density techniques whereas analogue or mixed signal elements (such as an embedded wireless capability) – which are tough to fabricate using leading edge processes  – could be manufactured on a separate layer at a more relaxed process node. Third, 3D chips are much more difficult to reverse engineer, because upper layers hide those beneath.

A final key advantage is in time-to-market. At the Electronic Design Process Symposium, held in Monterey, California last year, Rahul Deokar, a Product Marketing Manager with Electronics Design Automation (EDA) vendor Cadence, summarised this benefit.

According to Deoker, at the 65-nm process node, it takes up to eight months to ramp production to high volumes. At 45 nm, it takes about a year. At 28 nm, it’s taking much longer, perhaps twice as long as a 65-nm design.


Figure 2: Cost reduction compared to previous manufacturing node. At 22 nm costs threaten to increase due to the requirement for double-pattern lithography

Manufacturers are now starting to think about the 22-nm node (22-nm is the distance of just 220 helium atoms place side-by-side) but, according to International Business Strategies, a industry analyst, they may need to think again because 22 nm is the first time the cost of transistors will actually rise again because of the need for a double-pattern chip fabrication process (see figure 2). 

“It’s clear that you cannot ride the IC process road map and shrink time-to-market,” says Deokar.

He notes that for a typical consumer product, a 6-to-9 month delay translates into about US$5 billion ($4.73 billion) in lost revenue, so the financial implications of the pursuit of Moore’s Law in the 2D domain are substantial. Figure 3 shows how the costs of System-in-Package (SiP) (non-TSV 3D ICs) and 3D ICs compare in terms of cost and performance with 2D devices.   

A different design dimension

 If 3D ICs apparently hold all the aces then why are chipmakers still pursuing Moore’s Law? The answer is because 3D chips are tough to design and difficult to make.

Even with the aid of modern EDA packages laying out a modern 2D chip is challenging. With a 3D device the problem is made much harder because each layer needs to be designed and then those layers need to be connected by potentially thousands of TSVs. The complexity can be positively Gordian Knotesque – which is one of the reasons that current 3D chip designs are limited to just two layers (typically a processor on the bottom connected to a memory chip on top). 


Figure 3: Cost and performance comparison between SiPs, 3D ICs and 2D devices

But routing complexity is only the start of the job for a budding 3D chip designer; according to Sachin S. Sapatnekar of the University of Minnesota, another design concern is that the large number of active devices packed into a small volume pushes up the power density compared to a corresponding 2D circuit. As a result, hot spots can escalate unless thermal issues are considered at every stage of the design process.

Sapatneker suggests the thermal issue should be addressed by judiciously positioning thermal vias within the layout. He explains that these vias correspond to intertier metal connections that have no electrical function, but instead, constitute a passive cooling technology that draws heat from the problem areas to a heatsink.

EDA software firm Cadence has released a whitepaper summarising the challenges of 3D design entitled “3D ICs with TSVs—Design Challenges and Requirements”. In the paper, the company notes that the main problem with 3D-chip development is coordinating the IC and package design. The firm suggests that if the chip, package and board are not designed cooperatively, the interconnections will not be optimised, and extra vias will be needed to handle signals that cross from one point to another. As a result, performance will be reduced, additional board layers may be needed, and board and package costs may rise.

Cadence goes on to explain that IC and package co-design is especially important for 3D ICs because there are a large number of I/Os, and because the cost of packaging increases when multiple dies are incorporated into one package. The company says without co-optimisation, the package could end up costing more than the die.

In addition, 3D die stacks result in many more interconnections than 2D devices and many of these have to be connected to the PCB. The board designer needs to work out the best place to put the 3D package relative to the rest of the components on the board so that he can position and rotate components properly in order to accommodate the 3D package interconnect but minimise the number of layers required for the PCB.

There is one advantage that contemporary 2D-chip design brings to 3D-IC development. Digital designers and their RF/analogue peers have traditionally eyed each other suspiciously over the office partition, but the advent of 2D system-on-chip (SoC) products has forced them to work together as each circuit type often sits adjacent on the same die. So, working to optimise separate layers of a 3D chip should be just an extension of that established practice.

Adapting established EDA software to the challenges of 3D IC design – especially for chips that will venture beyond the modest two layers currently in vogue – is a different matter.

Cadence is putting its money where its mouth is by entering into a collaboration with silicon foundry Taiwan Semiconductor Manufacturing Company (TSMC). The two companies claim they’ve worked together to “create and integrate features to support this new type of design, culminating in the test-chip tapeout of TSMC’s first heterogeneous Chip-on-Wafer-on-Substrate [3D IC] vehicle”.

“In 2012 3D IC became a viable option for real-world chip design,” claims John Murphy, group director, Strategic Alliances at Cadence. “For 10 years, Cadence has invested in SiP and 3D IC design capabilities. Now we can share this knowledge with designers to bring this versatile technology to market.”

Cadence’s main rivals, Synopsys and Mentor Graphics, are also chasing a share of this specialised but growing sector.

Synopsys launched a 3D- IC solution in the first half of 2012. The company claims its Sentaurus Interconnect TCAD tool analyses the effects of the different CTEs of the layers and the stress around TSVs “enabling performance and reliability optimization”. The plan is for foundries to use the modelling results to specify design rules for 3D-IC integration to ensure manufacturability and reliability.

“[Some] reported benefits, such as improving time-to-market, lowering risk and lowering cost, still need to be realised before 3D-IC integration becomes a commercially viable alternative to traditional 2D architectures,” noted Phil Marcoux, Managing Director at consultants PPM Associates, in a statement. “The availability of Synopsys’ silicon-proven EDA and IP solutions is an important contribution to deploying 3D-IC integration technology.”

Wally Rhines, Chairman and CEO of EDA vendor Mentor Graphics also highlights the embryonic state of 3D-IC software. Speaking at a seminar on 3D-IC challenges last year, Rhines noted that the step from 2D to 3D chips is likely to be driven by the cost advantages of the stacked designs – but will be drawn-out.

“The early adoption of 3D ICs will be driven by performance, power and form factor,” he said during his presentation. “But the transition is likely to take time and will be achieved via 2.5D ICs and the design methodology will change in an evolutionary, rather than revolutionary, manner.”

For its part, Rhines’ company offers, among other services, a 3D-IC prototyping service.

“We’re working with [chip fabricator] Tezzaron and [prototype service firm] MOSIS to ensure that even at the prototype stage our customers will be able to access production-certified [EDA software] Calibre solutions to verify that their 3D-IC designs are manufacturable,” said Joseph Sawicki, a VP with Mentor Graphics, in a statement.

Mentor Graphics says customers can use the 3D-IC service to create “proof-of-concept ICs that demonstrate the use of high-density TSVs in stacked die configurations for intelligent sensor, multicore processor and many other applications”.

TSVs test manufacturers

If chip companies can crack the design challenges there are several options for putting 3D ICs together. The so-called monolithic technique comprises forming all the circuits on layers on a single wafer, which is then diced into 3D ICs. Because there is only one substrate, there is no need for aligning, thinning, bonding or even TSVs. But this technique is only at the research stage and it’s hellishly difficult today to produce even simple working devices.


Figure 4: FEA plot shows how TSVs introduce stresses into the 3D IC

A more practical technique is wafer-on-wafer. Using this method, layers are formed on two or more wafers, which are then aligned, bonded and diced into 3D ICs. The TSVs are either built into the wafers before bonding or else created in the stack afterwards. The manufacturing is a little easier than monolithic technology, but yield is still a big problem as if any of the bonded layers are defective, the whole chip has to be discarded.

The die-on-wafer method is similar to wafer-on-wafer, except one wafer is diced and each die is then aligned and bonded onto die sites of the second wafer. As in the wafer-on-wafer method, thinning and TSV creation are performed either before or after bonding. The technique does alleviate the pressure to precisely align the two wafers of the wafer-on-wafer method, but takes much longer because of the individual placement of each die.

The final contemporary technique is die-on-die. In this method, the circuits are formed on multiple die and TSV creation may be done before or after bonding. One advantage of die-on-die is that

each die can be tested first, so that one bad die does not ruin an entire stack. In addition, each die in the 3D IC can be characterised before bonding, so that it can be mixed-and-matched with others to form a stack with optimised power consumption and performance.

Although these techniques are challenging, in principle they aren’t that far removed from the processes used to fabricate conventional chips – so in theory it should be feasible to tune them for cheap mass production. But the theory is one thing, forming the TSVs is quite another.

TSVs are relatively large compared to other features on the chip and can sometimes penetrate through all the active and substrate layers of the device. Worse still, the TSVs are made from copper and the chip bulk material is made of silicon – which have widely different CTEs.

The result is that TSVs set up both mechanical and thermal stresses in a delicate stacked chip that comprises features as small as tens of nanometres that are easily damaged.  

But that’s not all; the stresses due to TSVs cause the adjacent silicon lattice to deform, affecting the mobility of the electrons in the semiconductor and changing the electrical characteristics of the chip in unpredictable ways.

Finite element analysis (FEA) can be used for a detailed analysis of the effects of a single TSV (see figure 4), but is impractical for full-chip scale that may have thousands of such interconnects. The pressure is really on the EDA vendors to keep working on the development of cost-effective software to allow engineers to resolve the challenges presented by TSVs.

More of Moore’s

The 3D IC is small but growing. According to Texas-based analyst Markets&Markets, the global 3D IC market will grow from US$2.21 billion ($2.09 billion) in 2009 to US$6.55 billion ($6.19 billion) in 2016 and at a compound annual growth rate (CAGR) of 16.9 percent from 2011 to 2016. That compares with a global semiconductor market worth just over US$300 billion ($283 billion) in 2011.

The analyst firm recognises it’s early days noting “companies in this market need to efficiently balance their expenditure between capacity expansion and technology advancement … since the market for 3D ICs is yet to gain complete recognition and its successful penetration into different end-user segments is largely governed by the R&D initiatives”.

So expect chip-makers to carry on proving Gordon Moore’s prediction to be spot-on – at least for the immediate future – by fabricating even denser conventional chips. But in parallel be prepared for a steady rise into key applications by 3D ICs where their performance advantages make it cost-effective to turn to the new technology in preference to today’s 2D products.

That’s assuming, of course, that EDA companies and designers alike can get to grips with the unenviable task of mapping out complex chips in three dimensions. That job could make taming errant electrons look as simple as herding sheep.