Deepak Sekar, the chief scientist of MonolithIC 3D, has said in a blog that we are approaching limits for miniaturising CMOS transistors, but these limitations can be overcome.
According to Sekar, direct source-drain tunnelling is widely believed to be the fundamental limit for reducing the size of MOSFET features.
The 10 to 5nm node projected to be the point at which direct quantum-mechanical tunnelling kicks in, at which point further scaling down becomes impossible.
Sekar cited a possible solution arising from the use of a device structure called recessed channel MOSFET. In this strategy, the effective channel length is longer than the minimum feature size to reduce leakage.
“For CMOS logic transistors, when we approach the direct source-drain tunneling limit, we could move to recessed channel devices and use channel lengths longer than the minimum feature size,” Sekar wrote. “This could allow us to continue miniaturization and increase component density.”