Monitoring stresses on wafers during fabrication


IT IS now possible to measure physical changes in silicon while it is being processed into microelectronic devices, which could help improve fabrication techniques for even smaller circuits.

Semiconductor fabs are always looking to push the physical limits of wafers, making them ever thinner in order to pack more computing power into smaller devices.

However, thinner wafers are more brittle and prone to warping or breaking especially during processing when they are turned into devices.

Fabrication processes can involve bombarding the wafer with a beam of ions, dipping it in corrosive acids to etch tiny structures, exposing it to plasmas for cleaning, or coating it in layers of hot metal to create electrical contacts. Then, the wafer must be fixed into a package. All of this can put a lot of stress onto a thin sheet of silicon wafer.

But now fabs can gain visibility into the performance of the wafers during these processes, with Xiaowu Zhang, a researcher at the A*STAR Institute of Microelectronics, Singapore, developing a technique for measuring the stress in those chips during production.

Zhang and his co-workers designed and built stress sensors directly onto a silicon wafer to monitor the strain that such packaging exerts. The technology takes advantage of the piezoresistive effect in silicon — when a force is applied to a silicon wafer, it pushes atoms closer together.

This change in atom distribution alters the way an electrical current passes through the material, which can be measured as a change in resistance.

Each of the 17 stress sensor on the surface consists of 16 resistors. Since the piezoresistive properties of silicon are well known, Zhang and his co-workers could simply convert the changes in resistance to a corresponding change in stress.

Thus far, the technique has been tested in processes like thin-film coating, attaching a solder ball, drop-tests, etc. They are working to make the technique viable in through-silicon via processes.